ZeqChipDesign

IC timing analysis with HulyaPulse clock tree. Setup/hold verification at 0.777s boundaries, gate-level simulation, power estimation with R(t) leakage modeling.

Endpoint	POST /api/hardware/chip
Auth	api-key
Rate limit	10/min
Category	hardware

Parameters

Name	Type	Required	Description
netlist	object	Yes	Gate-level netlist (Verilog JSON or SPICE reference).
clockFreq_MHz	number	No	Target clock frequency.
processNode_nm	number	No	Fabrication node in nm.

Returns

{ setupSlack_ns, holdSlack_ns, powerEstimate_mW, criticalPath, drc_errors, zeqond }

Example

curl -sS -X POST \
  -H "Authorization: Bearer zsm_..." \
  -H "Content-Type: application/json" \
  -d '{
  "netlist": {},
  "clockFreq_MHz": 100,
  "processNode_nm": 7
}' \
  "https://zeqsdk.com/api/hardware/chip"

This protocol is a named building block — one of the operations you compose inside a state contract. Call it directly with the request above, or invoke it from a contract that fires on your machine's clock. Browse the whole library at GET /api/protocols; fetch this one at GET /api/protocols/zeq-chip-design.